1. Field of the Invention
The present invention relates to a ball grid array semiconductor package, and more particularly, to a ball grid array semiconductor package in which the number of connection pins are increased by improving the structure of a lead.
2. Description of the Related Art
In the semiconductor industry, Ball Grid Array (BGA) technology is often used to package semiconductor chip. Typically, in a BGA, a semiconductor chip is connected to an end portion of an inner lead and a bump is attached on the bottom surface of the lead. The bump is electrically connected with the terminal on a circuit board through a ball installed on the outer surface of a package mold.
FIG. 1 shows the structure of a conventional BGA semiconductor package. In a semiconductor device 30, a semiconductor chip 35 is installed on the upper surfaces of end portions of lead frames 33 and 33'. A gold wire 37 connects an electrode of the chip 35 and each of the lead frames 33 and 33'. Bumps 39 and 39' are installed at the respective lead frames 33 and 33'. The bottom surfaces of the bumps 39 and 39' are exposed to the outside of the lower surface of a resin mold 36. When the semiconductor chip 35 is mounted on a printed circuit board (PCB), a ball (not shown) is interposed between a port of the PCB and the respective bumps 39 and 39' and then melted to bond the same to each other.
FIG. 2 shows the bottom surface of the BGA semiconductor package. Here, the resin molding is removed from the package.
Referring now to FIG. 2, a plurality of lead frames 41, 42, 43, 44, 41', 42', 43' and 44' are attached on the bottom surface of the chip 35. Bumps 45, 46, 47, 48, 45', 46', 47' and 48' are attached on the leads 41-44', respectively.
As shown in FIG. 2, bumps 45, 46, 47 and 48 are not aligned in a straight line. Rather adjacent bumps are offset from each other by a predetermined distance. Likewise, bumps 45', 46', 47' and 48' are not aligned in a straight line, and adjacent bumps are offset from each other by a predetermined distance. Such a layout increases the number of lead frames that can be connected to the chip 35, and thereby increases the effective area on the PCB that can be utilized to connect the lead frames.
Although, the above described layout increases the number of lead frames that can be connected onto the surface of a PCB, further improvement is desired in the structure of the lead frames as well as the bumps that would allow for an even further increase in the number of lead frames that can be connected to the chip.